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  1. 74HC174B1 Hex D Flip-Flops with Clear DIP16

    74HC174B1 Hex D Flip-Flops with Clear DIP16

    € 0,55

    These edge triggered flip-flops utilize advanced silicon-gate
    CMOS technology to implement D-type flip-flops. They pos-
    sess high noise immunity, low power, and speeds compara-
    ble to low power Schottky TTL circuits. This device contains
    6 master-slave flip-flops with a common clock and common
    clear. Data on the D input having the specified setup and
    hold times is transferred to the Q output on the low to high
    transition of the CLOCK input. The CLEAR input when low,
    sets all outputs to a low state.
    Each output can drive 10 low power Schottky TTL equiva-
    lent loads. The MM54HC174/MM74HC174 is functionally
    as well as pin compatible to the 54LS174/74LS174. All in-
    puts are protected from damage due to static discharge by
    diodes to VCC and ground.

    Meer info
  2. 74HC273 Octal D-type flip-flop with reset; positive-edge trigger DIP20

    74HC273 Octal D-type flip-flop with reset; positive-edge trigger DIP20

    € 0,55

    ■ Ideal buffer for MOS microprocessor or memory
    ■ Common clock and master reset
    ■ Eight positive edge-triggered D-type flip-flops
    ■ Complies with JEDEC standard no. 7A
    ■ ESD protection:
    ◆ HBM EIA/JESD22-A114-C exceeds 2000 V
    ◆ MM EIA/JESD22-A115-A exceeds 200 V

    Meer info
  3. 74HCT374 Octal D-type flip-flop positive edge-trigger  3-state DIP20

    74HCT374 Octal D-type flip-flop positive edge-trigger 3-state DIP20

    € 0,50

    • 3-state non-inverting outputs for bus oriented applications
    • 8-bit positive, edge-triggered register
    • Common 3-state output enable input
    • Independent register and 3-state buffer operation
    • Output capability: bus driver

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  4. CD40105BE LOGIC FIFO REGISTER  DIP16

    CD40105BE LOGIC FIFO REGISTER DIP16

    € 1,15

    IC, 4 X 16 ASYNC FIFO REGISTER, DIP-16;

    FIFO Function:Asynchronous;

    Supply Voltage Min:3V;

    Supply Voltage Max:18V;

    Logic Case Style:DIP;

    No. of Pins:16;

    Frequency:8MHz;

    Memory Organization:16 x 4;

    Operating Temperature Min:-55°C ;

    RoHS Compliant: Yes

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  5. CD74HC238E High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting DIP16

    CD74HC238E High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting DIP16

    € 0,65

    The  ’HCT238 is a high-speed
    silicon-gate CMOS decoders well suited to memory address
    decoding or data-routing applications. Both circuits feature
    low power consumption usually associated with CMOS
    circuitry, yet have speeds comparable to low-power Schottky
    TTL logic. Both circuits have three binary select inputs (A0,
    A1, and A2). If the device is enabled, these inputs determine
    which one of the eight normally high outputs of the
    HC/HCT138 series go low or which of the normally low
    outputs of the HC/HCT238 series go high.
    Two active low and one active high enables (E1, E2, and E3)
    are provided to ease the cascading of decoders. The
    decoder’s eight outputs can drive ten low-power Schottky
    TTL equivalent loads.

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  6. CD74HC257E - High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs DIP16

    CD74HC257E - High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs DIP16

    € 0,90

    • Buffered Inputs
    • Typical Propagation Delay ( In to Output ) = 12ns at Vcc = 5V, CL = 15pF, TA = 25C
    • Fanout (Over Temperature Range)
    - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
    • Wide Operating Temperature Range . . . -55C to 125C
    • Balanced Propagation Delay and Transition Times
    • Significant Power Reduction Compared to LSTTL Logic ICs

    Meer info
  7. DS1307 RTC Real Time Clock DIP8

    DS1307 RTC Real Time Clock DIP8

    € 2,45

    The DS1307 serial real-time clock (RTC) is a lowpower, full binary-coded decimal (BCD) clock/calendar
    plus 56 bytes of NV SRAM. Address and data are
    transferred serially through an I2C, bidirectional bus.
    The clock/calendar provides seconds, minutes, hours,
    day, date, month, and year information. The end of
    the month date is automatically adjusted for months
    with fewer than 31 days, including corrections for leap
    year. The clock operates in either the 24-hour or 12-
    hour format with AM/PM indicator. The DS1307 has a
    built-in power-sense circuit that detects power failures
    and automatically switches to the backup supply.
    Timekeeping operation continues while the part
    operates from the backup supply

    Meer info
  8. HCF4007UBE - DUAL COMPLEMENTARY PAIR PLUS INVERTER DIP14

    HCF4007UBE - DUAL COMPLEMENTARY PAIR PLUS INVERTER DIP14

    € 0,55

    .STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
    .MEDIUM SPEED OPERATION tPHL, tPLH =30ns (typ.) AT 10V
    .QUIESCENT CURRENT SPECIFIED TO 20VFOR HCC DEVICE
    .INPUT CURRENT OF 100nA AT 18V AND 25°C
    FOR HCC DEVICE

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  9. HCF40105BE FIFO REGISTER DIP16

    HCF40105BE FIFO REGISTER DIP16

    € 1,15

    HCF40105B is a monolithic integrated circuit
    fabricated in Metal Oxide Semiconductor
    technology available in DIP packages.
    HCF40105B is a low power first-in-first-out (FIFO)
    "elastic" storage register that can store 164-bit
    words. It is capable of handling input and output
    data at different shifting rates. This feature makes
    it particularly useful as a buffer between
    asynchronous systems. Each word position in the
    register is clocked by a control flip-flop, which
    stores a marker bit. "1" signifies that the position’s
    data is filled and "0" denotes a vacancy in that
    position. The control flip-flop detects the state of
    the preceding flip-flop and communicates its own
    status to the succeeding flip-flop. When a control
    flip flop is in the "0" state and sees a "1" in the
    preceding flip-flop, it generates a clock pulse that
    transfers data from the preceding four data
    latches into its own four data latches and resets
    the preceding flip-flop to "0". The first and last
    control flip-flops have buffered outputs. Since all
    empty locations "bubble" automatically to the input
    end, and all valid data ripples through to the output
    end, the status of the first control flip-flop
    (DATA-IN READY) indicates if the FIFO is full, and
    the status of the last flip-flop (DATA-OUT READY)
    indicates if the FIFO contains data. As the earliest
    data is removed from the bottom of the data stack
    (the output and), all data entered later will
    automatically propagate (ripple) toward the
    output.

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  10. HCF4521B 24 STAGE FREQUENCY DIVIDER DIP16

    HCF4521B 24 STAGE FREQUENCY DIVIDER DIP16

    € 0,70

    ■ VERY LOW QUIESCENT CURRENT
    ■ HIGH NOISE IMMUNITY
    ■ VOLTAGESUPPLYRANGE 3V TO 18V
    ■ ALL STAGES ARE RESETTABLE
    ■ RESETDISABLES THE RC OSCILLATORFOR LOWSTANDBY POWER DRAIN
    ■ RC AND CRYSTAL OSCILLATOROUTPUT ARE CAPABLEOF DRIVING EXTERNAL LOADS

    Meer info

Artikelen 1 tot 10 van 34 in totaal

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